This invention is generally related to an embedded dynamic random access memory (embedded DRAM), and more particularly, to a concurrent refresh mode and design which employs distributed row address counters integrated in each DRAM.
Improvements in semiconductor technology have enabled the design of processors having performance exceeding 1 Giga Hz. However, the system performance is often constrained by the performance of its memory. The presence of this drawback has created a potentially strong demand for high performance embedded DRAMs to help the processor achieve the necessary speed. For 90 nm technology generations and beyond, it is difficult to reduce the cell size and still improve the array access transistor performance of the embedded DRAM. This is true because the transistor threshold voltage cannot be reduced when device leakage is present. Yet, the operation voltage must be reduced to guarantee the device reliability and logic process compatibility. These considerations have created a fundamental shift from a data retention driven design to a memory availability driven design by utilizing a high performance logic device as a memory cell.
Referring to FIG. 1, there are shown simulated sensing signals illustrating the aforementioned assertions. In the plot referenced (A), a conventional array device 52A (not shown) having a 2.5 V wordline boosted voltage (VPP) and supported by a long bitline coupling 256 cells (256 b/BL) is compared to the plot referenced (B), wherein a logic array device 22A (not shown) powered by a 1.5V VPP is supported by a short bitline coupled to 64 cells. The sensing signal is extracted by changing the signal development time (tSIG), i.e., the time to develop a signal on the bitline when a wordline is activated over a random access cycle time (tRC) in a grounded sensing scheme. As the signal development time increases, an excess of charge in the cell is transferred to the bitline, increasing the sensing signal. However, when tSIG is incremented by more than about 40% of tRC, the voltage is not adequately written back to the cell, resulting in a smaller signal. Since the logic array device 22A is enabled by approximately 30% more current than that applicable to the corresponding array device 52A, approximately 80 mV of the sensing voltage can be achieved even for a 3.2 ns random access cycle time. However, employing a logic array device 22A requires a reduction in the data retention time to a value as small as 64 μs. The shorter retention time greatly reduces the memory availability, particularly for a large density memory because all the memory cells need to be refreshed within a given retention time to maintain the data bits. By way of example, a 4 Mb memory having 8K wordlines requires 8K refresh cycles within 64 μs. This, in turn, requires at least one refresh command every 8 ns, resulting in the memory being unavailable for an 8 ns random cycle memory. In order to overcome the memory availability problem in short retention DRAMs, a concurrent refresh mode is typically used, as described, e.g., in U.S. Pat. No. 4,185,323 issued to Johnson et al.
FIG. 2 is a block representation of a semiconductor memory chip 200 consisting of a plurality of DRAM memory banks 210. Each memory bank 210 consists of a plurality of DRAM memory cells (not shown) arranged in a two-dimensional matrix configuration, well known in the art, and which, accordingly, will not be discussed further. Once a memory access operation (read, write, or refresh operation) is initiated in a DRAM bank 210 (e.g., 210i), the DRAM bank (e.g., 210i) becomes unavailable for a random access cycle time tRC. During the memory access operation of the DRAM bank (e.g., 210i), other DRAM banks (e.g., 210j) can be simultaneously refreshed. Thus, the memory availability greatly improves by concurrently performing a refresh operation while enabling a memory access operation. There are two known methods for enabling a concurrent refresh mode in a semiconductor memory, the details of which will be discussed hereinafter, as explained hereinafter with reference to FIGS. 3 and 4.
FIG. 3 illustrates a first method to enable a concurrent refresh mode in a conventional static random access memory (SRAM) buffer. Details of this approach are described, e.g., in U.S. Pat. No. 5,999,474, issued to Leung et al. Semiconductor memory chip 300 consists of a plurality of DRAM banks (310DRAM), each consisting of a plurality of memory cells arranged in a two dimensional array configuration. Accessing bank 310DRAM-310j while concurrently refreshing at least one other bank 310DRAM-310k is possible as long as the accessed bank and the refreshed bank differ from one another. This allows a plurality of cells (330k) supported by the corresponding wordline 320k in DRAM bank (310k) to be refreshed while accessing a plurality of cells (330j) supported by the corresponding wordline (320j) in the DRAM bank (310j). However, if array 310j is continuously addressed, some memory cells within the same array 310j will not be refreshed altogether since array 310j is continuously busy due to an uninterrupted memory access operation. This precludes performing a refresh operation of some memory cells in the same array (310j).
In order to overcome this problem, memory chip 300 is enhanced by adding an SRAM bank (310SRAM), featuring a dual port function that allows receiving and transferring data within a clock cycle. The access operation of the DRAM banks (310DRAM) and SLAM (310SRAM) are controlled by the TAG memory (310TAG), while the memory access of the memory chip 300 is enabled by a read or write command (not shown), a bank address (XBADD), and a word address (XWADD), wherein XBADD and XWADD identify one of the DRAM banks (310DRAM) and the appropriate wordline within the selected DRAM banks. When the memory access is enabled, wordline (320TAG) in the TAG memory (310TAG) and the wordlines (320s) in SRAM bank (310SRAM) are activated by decoding the word address (XWADD). This enables reading out data in the memory cells (330TAG) in within the TAG memory (310TAG) and data in the memory cells (330s) within the SRAM buffer (310SRAM). The read data bits (330TAG) of the TAG memory (310TAG) defines the bank address (TBADD) which, in turn, identifies the corresponding DRAM bank for the data bits (330s) currently read from the SRAM buffer (310SRAM). When TBADD coincides with the bank address input (XBADD), the data bits (330s) are the ones that are requested by the memory access command, since the data bits (330s) were previously copied from the corresponding DRAM bank to the SRAM buffer (310SRAM). Therefore, no DRAM bank access is necessary, and the read data bits from the SRAM buffer (310SRAM) are read am from the XDATA pins. On the other hand, if TBADD differs from the bank address inputs (XBADD), the TAG memory (310TAG) control the DRAM banks (310DRAM) as follows.
Assuming that TBADD identifies DRAM bank (310i), then, the data bits (330s) in the SRAM buffer (310SRAM) are stored back in DRAM bank (310i), where the wordline 320i is same as the wordline address of 320s (Direct Mapping). This allows data bits to be transferred from the SRAM memory cells (330s) to the DRAM memory cells (330i). Concurrent with the bank address input (XBADD), the corresponding DRAM bank (310j) is activated for a read operation. Then, the cell's data bits (330j) in the corresponding DRAM bank (310j) are read out, where wordline 320j coincides with the wordline address of 320s (Direct Mapping). They are read am from the XDATA pins. The cell's data bits (330j) are also stored in the cells (330s) of the SRAM buffer (310SRAM) TBADD is therefore updated to identify the DRAM bank 310j for a future memory access command. For a subsequent same addressing pattern (i.e., 330j), data bits are read out or written into the SRAM buffer (310SRAM), enabling a refresh operation of the memory cells even when only one array (i.e., 330j) is continuously addressed. This is possible since, eventually, the data bits in the array will be copied to the SRAM array, refreshing the array without infringing on any violations.
This concurrent refresh approach, however, has several drawbacks. First, it requires an SRAM array (310SARM), which is significantly larger. Secondly, on account of the TAG management, the logic becomes more complex which, in turn, slows down the latency of the memory access. Finally, this methodology is not appropriate for multi-bank memories since the memory bank becomes unavailable during a refresh operation within a given DRAM bank cycle (tRC). Multi-bank memory chips require addressing any bank that need to be addressed during each bank-to-bank access cycle (tRRD)—which is shorter than tRC—making it impossible to enable a refresh operation when a tRC cycle is required.
FIG. 4 illustrates the second method that enables a simultaneous refresh by utilizing a concurrent function for the DRAM. Semiconductor memory chip 400 consists of a plurality of DRAM banks 410 (410i through 410j), each of which is controlled by the corresponding address and command ports (420i through 420j). Therefore, any two or more banks can be activated concurrently. By way of the concurrent function, memory bank 410i remains in the read mode while still enabling a refresh operation for memory bank 410j. However, this approach requires a complex refresh system management to avoid a bank access contention caused by the concurrent function. While avoiding a bank access contention by the concurrent function, handling the refresh addresses in each array at the system level is highly complex since the address TAG for the refreshed memories for all the banks needs to be independently managed. As a result, employing the concurrent function for a simultaneous refresh requires significant system modifications.